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This is an archive of release notes of each build. The following build numbers are for Version 1.5. Note that build numbers restart with every release of the software. Only builds that were released to the general public are documented here.

What is new in Build #17: August 18, 2001

  • This is the final release build for VHDL Simili Version 1.5

What is new in Build #16a: June 12, 2001

  • BugFix: The simulator crashed when the -G option was used with a generic name that was part of an entity but was not directly referenced in the generic map in the instantiation. This is now fixed.

What is new in Build #16: June 10, 2001

  • BugFix: The compiler did not allow indexed names where the index involved function calls in individual port-map associations.
  • BugFix: The compiler did not allow an OTHERS on a non-locally-static aggregate type even if the rest of the aggregate choices were not named-associations (the compiler was overly strict).
  • BugFix: There was an error in optimizing boolean expressions involving std_logic constants which under certain circumstances, produced an erroneous result.
  • BugFix: SDF annotation was not possible if the target instance was nested inside an if/for generate block.
  • BugFix: The simulator crashed during elaboration if an unconstrained port was initialized with an unconstrained generic which did not have a default value.

What is new in Build #15a: May 23, 2001

  • BugFix: The compiler did not allow indexed names where the index involved function calls in the sensitivity list. This is now allowed.
  • A couple of minor edits were made to the documentation

What is new in Build #15: May 21, 2001

  • BugFix: The compiler incorrectly allowed the use of OTHERS in an aggregate when the type of the aggregate was a non-locally-static type. Although the simulator and the compiler handled this case as expected, we have decided to disallow this since the language specification forbids such a use of OTHERS.
  • BugFix: The compiler failed when a type-name (such as "bit") was used as a array-type-port-name in a component and if the instance of such a component has individual named associations (such as bit(7) => mysig) in the port-map.
  • BugFix: The compiler failed to compile a record-aggregate with named associations where a record-field name and an enumeration literal with the same name were visible at that point.
  • BugFix: There was an error in subtype-checking for integer signals (not variables) where the subtype of the integer was determined by generics and such an entity/architecture was instantiated more than once.

What is new in Build #14: Mar 31, 2001

  • User contributions: There are now two VCD translators available on the contribs page. These utilities can be helpful in being able to see waveforms. These utilities will work with both 1.4 and 1.5 releases.
  • BugFix: The simulator crashed when an architecture that contained a scalar type-conversion in the port-map was instantiated more than once. This has been fixed
  • BugFix: The compiler did not allow 'ascending attribute on an array. This is now supported. The 'ascending can now be used on scalar types, constrained array types and any array variable.

What is new in Build #13: Mar 21, 2001

  • Improvement: The compiler and the simulator have been enhanced to now support port/generics in block statements.
  • BugFix: The compiler crashed when a multi-dimensional array was initialized using string literals for the inner dimensions -- This is a regression since Release 1.4 and has now been fixed.
  • BugFix: Using Xilinx simprim libraries, simulation results may have been wrong under some circumstances for post-route timing simulation (with SDF annotation) -- This is a regression since Release 1.4 and has now been fixed.

What is new in Build #12: Mar 7, 2001

  • BugFix: Under certain conditions, the initial value of a signal was wrong when it involved ports and multiple connections and multiple initial values (from the port map, the component and the entity). This has been fixed according to the rules of VHDL '93.
  • BugFix: A crash in the simulator was fixed due to a bug in the compiler. The compiler did not properly translate an array type definition that involved very complex expressions. The compiler (vhdlp) has been fixed to prevent this in the future.
  • BugFix: The simulator did not give correct results when nested guarded blocks were involved and when the "guard" signal from an upper scope was used in the definition or a nested (inner) "guard" signal. If such guard signals were used (even when nested) in other situations, this was not a problem. This problem has been fixed.

What is new in Build #11: Feb 20, 2001

  • Feature: The REPORT statement now responds to the -breakon option as well. Prior to this build, the -breakon option only affected the ASSERT statement.
  • BugFix: The simulator (vhdle) crashed when a signal was involved in more than one port-map with a function call on the actual part of a port-map.
  • BugFix: When a physical number was divided by a real number there was potential for a round-off error (because the division was occuring in fixed point). According to the VHDL spec, the division should happen in in the floating point domain and then the result is rounded to a integral value. This has been corrected.

What is new in Build #10: Jan 28, 2001

  • The Vital example (tutorial) was broken. This has been fixed.

What is new in Build #9: Jan 16, 2001

  • This is the first public build for version 1.5 since the production version 1.4 was made.
  • The release notes contain the list of changes from 1.4. Users with very large designs and Xilinx 3.1i users will see the immediate benefits of this version.

Build Updates for Version 1.4:

There are no updates as of this moment. While we transition into the next version, please watch this area for updates to 1.4. We will try our best to update 1.4 with important bug fixes. Please read below if you were a beta user of Simili 1.4.

Build Updates for Version 1.4 Beta:

What is new in Build #33 and #34: November 14, 2000

  • Build 34 is the final build of version 1.4. We would like to thank everyone who provided valuable feedback and help make VHDL Simili a better tool. We could not have done it without you.
  • BugFix: The reject clause within an intertial delay assignment did not work correctly. Fixed
  • BugFix: The '-g' option did not work under certain circumstances. Fixed.
  • BugFix: Wrong error message was printed when maximum number of delta-cycles were exceeded. Fixed.
  • BugFix: When a string literal contained an character in the range of 0x80-0xff, it crashed the compiler. With build#34, you can now safely use the entire range allowed by 8-bit ascii.

What is new in Build #32: August 8, 2000

  • BugFix: Type conversions on port-map's were not working correctly when the type-conversion was done via a function-call. This has been fixed and there is no easy or acceptable workarounds for previous builds.
  • Two new technical-notes have been created to document limitations of VHDL Simili that cannot be remedied in version 1.4.
  • BugFix: An attribute specification on an invalid component instantiation label caused the compiler to produce an internal error. With this build, you will get a proper error message instead of an internal error. For previous builds, fixing the semantic error in the VHDL code will prevent the internal error.

What is new in Build #31: July 25, 2000

  • Feature: In the VHDL87 mode, we now treat bit-string literals strictly as bit-vectors (in VHDL 93 bit-strings are essentially like overloaded constants like character literals and can be of any compatible type).
  • BugFix: The simulator crashed while trying to elaborate the use of an incomplete type. This has been fixed.
  • BugFix: Initalizing a deferred constant with an aggregate produced a false compiler error. This has been fixed.

What is new in Build #30: June 30, 2000

  • Feature: This build contains additional Synopsys packages that are shipped precompiled. These are ATTTRIBUTES, BV_ARITHMETIC, DISTRIBUTIONS, and SDF_HEADER. None of these new packages are accelerated, however, they might be useful in being able to compile models that refer to these packages.
  • BugFix: The was a bug in the accelerated version of the std_logic_arith package where in some cases, the result was all 'X's if one of the operands was a single bit (std_ulogic type). Workaround for previous builds is to use the "-noaccel std_logic_arith" option.
  • BugFix: In certain cases, user defined physical types with certain ranges caused an "Internal Error". This has been corrected. If you run into this problem with previous builds, there is no workaround.
  • BugFix: Configurations statements caused an "Internal Error" under certain conditions.
  • BugFix: When multi-dimensional arrays were passed as PROCEDURE arguments, access to the array elements was flawed (could only access a limited portion of the array correctly). There is no workaround for previous builds. Multi-dimensional arrays worked fine every place else.

What is new in Build #29: May 29, 2000

  • BugFix: A procedure with zero arguments failed to compile if the procedure was declared in a package and then later defined in the package body. This was not a problem with functions.
  • BugFix: The 'POS attribute on discrete types sometimes caused an internal error in the simulator. Specifically, the 'POS attribute failed if it was the direct target of an assignment.
  • BugFix: The implicit/predefined WRITE procedure (not the one in TEXTIO) had a bad signature. The 'value' parameter was declared as a VARIABLE instead of a CONSTANT which may have caused some false compilation errors. You would have seen this error only if you were declaring your own FILE types and were using the WRITE procedure with arguments that were objects other than variables.
  • BugFix: User defined physical types may have caused false subtype check errors.

What is new in Build #28: May 13, 2000

  • Feature: SDF annotated designs will see as much as 50% performance improvement in design elaboration time.
  • BugFix: The simulator failed during elaboration if an alias to a signal was involved in a port map. This has been fixed.
  • BugFix: In UNICODE versions (many Asian language versions) of the Window's OS'es, the compiler was unable to save modules whose names had extended identifiers. This have been corrected. This was not a problem with Engilsh (and other European languages) versions of the OS'es. You may wish to cleanup (remove) any existing .sym directories -- not required but recommended.
  • BugFix: Fixed an intermittent crash that would randomly occur on certain designs. This bug was not related to a particular design construct or compiler/simulator/library feature.

What is new in Build #27: Apr 29, 2000

  • Feature: Some changes have been made to the VHDL library structure to better allow VHDL Simili to work with the WINE -- the windows emulator under Linux. Windows user should NOT be affected by this change.
  • BugFix: Writing out real (floating point) numbers did not work when the 'digits' parameter to the std.textio.write procedure was non-zero.
  • BugFix: Under certain contains, the simulator exited without flushing the list output file. This happened if the simulator exited due to an exception caused by illegal VHDL or an ASSERTION failure. This was not a problem under normal conditions.

What is new in Build #26: April 16, 2000

  • Feature: You can now disable warnings emanating from the accelerated std_logic_arith package using the -nowarn option
  • BugFix: The simulator produced and internal error if the top level entity had unconstrained array ports.
  • BugFix: The std_logic_arith multiplication operator produced one fewer bits for a result if the types of the operands were not the same (one signed and another unsigned).

What is new in Build #25: April 3, 2000

  • Feature: You can now set generics for the entity/architecture you are simulating from the command line using the -gName=Value option. You can override the existing defaults from the command line for all scalar types and 1-dimensional character types (such as std_logic_vector, bit_vector, string, etc.)
  • Feature: The compiler now allows VHDL'87 style syntax for FILE types. You can enable VHDL'87 compatible mode using the -87 option on the compiler. When this option is enabled, the VHDL'87 syntax/semantics for FILE types are translated to their VHDL'93 equivalents. Please note that the use of this option is not recommended since the semantics of dealing with FILE types is much better defined in VHDL'93 and we recommend that you port your existing designs to the VHDL'93 style if possible.
  • Feature: VHDL Simili now supports Cypress' Warp 6.0. The scripts files have been updated to auto-detect Warp 6.0. Also, VHDL Simili no longer ships source files for the Cypress libraries. The script file has been updated to use your copy of these files.
  • Feature: VHDL Simili also ships with a GUI that aids in compilation/simulation tasks. Please visit out contributions area for more information
  • BugFix: The simulator did not correctly handle a slice to a slice assignment under the following condition -- the prefix of the two slices are the same and the array type is an array of an array and the assignment was essentially a left shift. Workaround for previous builds is to use a temporary to make the assignment.

What is new in Build #24: Mar. 19, 2000

  • BugFix: Use of a ".ALL" construct for an access type as an argument to a subprogram caused in internal error in the simulator during elaboration. Use of .ALL in other contexts was not a problem. This problem has been fixed.

What is new in Build #23: Mar. 6, 2000

  • Feature: Added an option -nostderr to the compiler and the simulator to force all output produced by these tools to go to stdout only. This is helpful in environments where it is not easy to redirect/capture both stdout and stderr to a file.
  • BugFix: The simulator produced an internal error in certain cases if the prefix of an attribute was not a simple name and if such an attribute existed in an entity/architecture with generics.
  • BugFix: The simulator required a real number to precede a time unit while reading in values of type time using textio. The simulator now allows an integer also.

What is new in Build #22: Feb. 26, 2000

  • BugFix: The simulator produced an internal error in certain cases where, in a guarded block, a slice of a guarded signal was the target of an assignment. This has been fixed in Build#22.
  • BugFix: The simulator produced an internal error if the actual of a port map in a component instantiation was a slice of an array, AND the architecture containing such a component instantiation was instantiated more than once.

What is new in Build #21: Feb. 12, 2000

  • Feature: VHDL Simili now supports "Negative Constraint Calculation" that is required as part of achieving full Vital/SDF compliance. Most vendors' Vital models do not need this feature. This feature may be necessary if you have Vital models that expect negative delays for setup, hold, recovery or removal type parameters.
  • Feature: VHDL Simili now supports the INTERCONNECT construct in SDF files (Atmel SDF files use this construct).
  • BugFix: If you use a qualified expression for a case expression of an array type, where the argument of the qualified expression was a slice of a non-constant range, it caused a fatal error in the compiler. This is fixed in Build#21. There is no acceptable workaround for previous builds.
  • BugFix: A signal assignment to a signal that is a formal parameter of a procedure, caused an internal error in the simulator IFF such a procedure was declared inside a process. This is fixed in Build#21. The workaround for previous builds is to move the procedure definition outside the process (to a package or the architecture scope).

What is new in Build #20a: Feb. 1, 2000

  • News: Build 20 now includes preliminary support for the Atmel FPGA devices using Atmel's IDS 6.0 software. We have also verified Build 20 for the Xilinx CPLD devices (both CoolRunner and 9500 Series devices).
  • BugFix: The semantics of the nand and nor operators were reversed for the bit/boolean data types. This was not a problem for any other type or even for bit/boolean arrays. There was no acceptable workaround for previous builds. This has been fixed.
  • BugFix: The compiler was overly strict in configuration specifications that occur inside architectures with regards to references to architecture names inside configurations (it  required that the architecture already be compiled). This has been fixed.

What is new in Build #20: Jan. 30, 2000

  • This build has been revoked because configurations statements declared inside architectures can sometimes trigger a false internal error. This build has been superceded by Build#20a.

What is new in Build #19: Jan. 24, 2000

  • BugFix: The 'stable attribute was not simulating correctly under certain circumstances. This has been fixed.
  • BugFix: The simulator did not handle functions that terminated without executing a RETURN statement in a graceful manner. You will now get a meaningful error message along with a stack trace.
  • BugFix: The compiler produced false errors when you have a port/generic map using named associations, and the name of the formal also happens to be a visible enumeration literal. For example, if you have a port/generic called ERROR or WARNING which are enumeration literals declared in the STANDARD package, you will not be able to associate such a port/generic using named associations. This problem has been fixed.

What is new in Build #18: Dec. 29, 1999

  • Feature: The command line and the command file only allowed integers in time specification. This has been changed so that you can now enter time units such as 0.1ns (before you would have had to say 100ps).
  • BugFix: In Build#17, some accelerated Vital simulations were producing an internal error. This has been fixed.
  • BugFix: The "wait until" construct used in a procedure may not have behaved as expected (was not a problem with "wait for" or "wait on"). This has been fixed.

What is new in Build #17: Dec. 13, 1999

  • Feature: It is officially here...You can now write command files that allow you to monitor signal values (and write them out to a file) anywhere in your design hierarchy. You can monitor simple scalar signals to very complex data types or portions there of. Click here to view documentation for this feature and see examples.
  • BugFix: A concurrent procedure call where the procedure being called invokes wait statements causes the simulator to produce an error. Workaround for previous builds is to enclose such a procedure call in an equivalent process (with a wait statement).
  • BugFix: Using a non locally static attribute expression while defining a subtype may have caused a compiler error. The workaround for previous builds was to define constant(s) initialized with such expression(s) and then using these constants to define a range of the subtype.

What is new in Build #16: Dec. 6, 1999

  • Feature: A 5% improvement in performance has been achieved. Designs using heavy use of arrays may realize an even greater performance improvement. Designs that are mostly structural with no vectors and/or subprogram calls involving vectors will see the same performance as before.
  • BugFix: A couple of bug fixes related to RECORD type objects have been made.
  • BugFix: In a case statement, a discrete range choice (such as "when 2 to 4 =>...") did not produce the expected behavior. This has been fixed.

What is new in Build #15a: Nov. 29, 1999

  • Build#15 may have been corrupted. This has been replaced by Build#15a. If you have Build#15, you might not have seen one or more of the bug fixes listed for Build#15.

What is new in Build #15: Nov. 28, 1999

  • With build #14, the size of the download had increased by almost a megabyte. With build#15, the download should be back at 2.3MB. To be able accomplish this, build #15 will use the Xilinx libraries that are already on your hard disk (under the Xilinx installation directories). We also added support for the Xilinx LogiBlox library.
  • BugFix: A concatenation involving two constants whose subtypes are not the same as the result causes an internal error. An inconvenient workaround exists for this problem (declaring one of the operands to be a variable or a signal).
  • BugFix: An integer/enum/real subtype declaration may crash the compiler if the range specified for the subtype contains expressions involving function calls (note that operators are also functions). The work around is to declare temporary constants for the expressions that are appearing in the range definition.
  • BugFix: Fixed a bug in the TEXTIO accelerated package where the printing of a bit_vector type was erroneous.
  • BugFix: The compiler did not allow a string type to be a case expression. This has been corrected.

What is new in Build #14: Nov. 23, 1999

  • Yes, we have heard the requests from the Xilinx community. This build supports the Xilinx UniSim and SimPrim libraries. We would like to thank Xilinx for providing us the necessary help in being able to do this very quickly.
  • BugFix: There was a problem with SDF back-annotation of generics related to vectored ports The SDF annotator complains of type mismatches when it should not.
  • BugFix: There was an error in the rules used to check for the validity of a wait statement inside a procedure. 
  • BugFix: The simulator (actually the code generator) hung when a type conversion from a subtype of an integer to a real was done.

What is new in Build #13: Nov. 14, 1999

  • Added a command line option to stop the simulator at a user specified severity. This feature is accessible through the -breakon command line option. Please see the updated documentation for more information.
  • BugFix: The simulator was producing an internal error when an aggregate was used as an actual of a generic map and the formal for such a generic was a non locally static type.
  • BugFix: The compiler was not using the proper lexical rules for based-integer-literals. When an exponent is not used, a based-integer-literal must now end with a '#' character (this is according to the rules of VHDL). The compiler now follows the rules set forth by the VHDL language specification.
  • BugFix: A case expression which was an indexed expression was not being allowed by the compiler if the index was not locally static. Now such an expression is allowed as a case expression as long as the type of the expression is locally static.
  • BugFix: The simulator was unable to parse in integers/reals correctly using file io. This has been corrected.
  • BugFix: The simulator sometimes produced an internal error upon closing a file multiple times. This has been fixed and it now issues a better error message.

What is new in Build #12: Nov. 8, 1999

  • We have added a second tutorial/example that demonstrates the use of VHDL Simili with Vital and SDF to perform post-layout simulation and to use the same test bench to perform pre-synthesis simulation.
  • BugFix: We may have uncovered a bug in our optimizer that can cause wrong simulation results. This bug affects all currently active builds but it shows up under extremely rare conditions. If you suspect that your simulations are not working as you expected, please use the -nocycleopt option. This has been fixed in the current build.
  • BugFix: A sliced/indexed expression whose prefix is a function call requiring overload resolution was not handled by the compiler. For example, myfunc(arg1,arg2)(7 downto 0) gave you a type mismatch error. Workaround for previous builds is to assign the result of myfunc(arg1,arg2) to a temporary variable and then take the slice of that variable.
  • BugFix: The code generator (simulator) use to complain erroneously about an array aggregate not having enough elements if this aggregate is formed with one choice and this choice is a discrete range that is not static. For example, (size-1 downto 0 => '0') caused a runtime error if 'size' was a variable or a signal). Workaround for previous builds is to do (others => '0') which essentially does the same thing and is more efficient.
  • BugFix: A FILE class parameter is was being flagged as error if the subprogram is being declared/defined in a package. Works fine if the subprogram is in an defined in an entity/architecture.

What is new in Build #11: Nov. 1, 1999

This build contains a major performance boost for designs using numeric_std and numeric_bit. It also contains several bug fixes.

  • Acceleration of the standard IEEE packages numeric_std and numeric_bit has been added. These packages were available in their normal un-accelerated interpreted form in previous releases/builds. You can expect a 10x performance improvement of designs using these packages. Acceleration of these packages can be disabled using the regular option (-noaccel). A new option was also introduced (-nowarn) to handle the suppression of warnings emanating from these packages. Please read the documentation on the simulator for more info.
  • BugFix: We have found a bug in Build#10 where if the prefix of a an array attribute was a function call, the compiler was erroneously flagging this as an error. For example, myfunc(arg1,arg2)'length would be flagged as an error in Build#10 (or earlier builds)
  • BugFix: The precedence of the unary +/- operators is wrong. The expression (-a + b) is erroneously interpreted as (-(a + b)) where the correct interpretation is ((-a) + b). However if the operator after 'a' is anything other than a binary '+' or a '-', then the expression is interpreted correctly.
  • BugFix: An expression of the kind type_conversion(qualified_expr'(...)) caused an internal error in the compiler. 
  • BugFix: Fixed a problem in accelerated version of std_logic_arith package where the "/=" operator was not working correctly. Workaround in previous builds was to use -noaccel stdlogicarith option.
  • BugFix: Fixed a crash in the compiler where if you invoked an operator using the function syntax "+"(a,b) (instead of the normal syntax of (a + b)). Most cases compiled okay but there was a potential for a crash if there were multiple design units in file.
  • BugFix: Signal attributes 'stable and 'quiet were not working under certain circumstances. They were being updated a cycle earlier than they should have been when they had a delay of zero time units. This is no longer a problem.
  • BugFix: When a slice was used in an actual of a port map where the formal was a port of mode IN/INOUT, this sometimes caused a fatal error.

What is new in Build #10: Oct. 20, 1999

  • Included in the build is a tutorial/example. There are a few other minor changes in documentation.
  • Vital acceleration has improved the simulator performance by about 30%.
  • Non-Vital simulator performance has also improved by about 15%.
  • The -p option now suppresses progress information instead of enabling it.
  • Preliminary support for guarded blocks has been added. Note that use of a guarded block in an unsupported way will be flagged as an error.
  • An internal limit causing an internal error has been remedied. The problem occurred if you had a process or a subprogram which contained more than 32,000 lines of code. You can now have an almost unlimited number of lines of code in a process or a subprogram. Such subprograms and processes were being created by other automated programs.
  • Fixed an bug in indexed expression where the prefix and the index was a constant. If the prefix was a string literal, it crashed the compiler and if the prefix was a constant name in an architecture (for example MyConst(3) where MyConst was a constant array) would have caused an internal error.
  • There was a bug in the Vital acceleration module where false glitches were reported. The results of the simulation were okay though.
  • A bug in the SDF annotation of a VITAL model has been fixed. This would have caused an incorrect setup hold violation in either accelerated or normal Vital simulations. In certain cases, the results of the simulation would have been wrong.

What is new in Build #9: Sept. 29, 1999

  • A bug in the std_logic_arith package acceleration was fixed. Signed multiplication was not working correctly when one of the operands was negative. This was not a problem if acceleration for std_logic_arith was disabled.

What is new in Build #8: Sept. 15, 1999

  • Fixed a bug in accelerated Vital procedure VitalPathDelay(...) where, in certain cases an improper delay was being calculated at time 0/delta 0. Simulation would ultimately agree with the non accelerated vital models (in most cases) but, at time 0/delta 0, the assignment to the driver was done with the wrong delay.
  • There was a bug that appeared when acceleration for the std_logic_1164 package was disabled. Depending upon the order of elaboration, certain functions defined in this package appeared to have no body thereby crashing the simulator.
  • The VHDL Simili Shell would not function as designed if there were spaces in the PATH of the existing environment (before the VHDL Simili Shell was launched). This condition is now handled.
  • Made some corrections in documentation.