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* The FREE Edition is targeted to the VHDL beginner/student, enabling simulation of small designs. It offers the full language support and design environment of the Standard edition, but has limited simulation capability. As design size grows (beyond a few hundred lines of VHDL code), the simulation performance of the Free Edition reduces almost exponentially. Symphony EDA reserves the right to change the terms and conditions of the Free Edition license at any time.
** The Standard Edition offers a complete development and run-time environment to users with "real-world" designs and basic simulation needs. It allows advanced waveform generation and eliminates the performance penalties of the Free Edition. Your purchased license gives you uninterrupted use of the software for a period of one year.
*** The Professional Edition is Symphony EDA's flagship product, offering maximum simulation performance and powerful design debug / verification features (including break points, signal force/release, and advanced code coverage). It addresses the needs of engineering teams and organizations developing multi-million gate ASIC or FPGA designs. With the Professional Edition, VHDL designers can iteratively validate and debug their RTL or post-layout netlists with fast runtimes; verification engineers can assess the quality of their test benches via code-coverage analysis; test engineers can automatically log and interpret coverage data over thousands of simulation runs in a test regression environment. With the Professional edition, you get a powerful simulation suite at less than half the cost of its commercial equivalents.

The following table contains a more detailed comparison of the feature set among the various editions.

Feature

FREE Edition Standard Edition Professional Edition
Language Features
    IEEE 1076-93 language support Yes Yes Yes
    Support for accelerated
        IEEE 1164 (std_logic) Yes Yes Yes
        IEEE 1076-3 (numeric_std, numeric_bit) Yes Yes Yes
        Synopsys Libraries (std_logic_arith, etc.) Yes Yes Yes
    Vital 1995/2000 (IEEE 1076.4) support with SDF 2.1, 3.0 and 4.0 Yes Yes Yes
Integrated Development Environment
    VHDL Aware project management Yes Yes Yes
    Automatic, continuous file ordering Yes Yes Yes
    Smart compile Yes Yes Yes
    Syntax highlighting Yes Yes Yes
    VHDL to HTML conversion Yes Yes Yes
    User configurable colors, preferences Yes Yes Yes
    Tcl console Yes Yes Yes
Simulation
    Waveform save/restore -- Yes Yes
    Compressed waveforms -- Yes Yes
    Waveform bookmarks -- Yes Yes
    Unlimited simulation time Yes Yes Yes
    Maximum number of waveforms 10 unlimited unlimited
    Ability to plot VHDL variables -- unlimited unlimited
    Simulation Speed Slow Normal FAST
    Global Optimizations -- -- Yes
    Vital Level1 Acceleration1 -- Yes Yes
    Vital Level0 Acceleration1 -- -- Yes
Debugging
    Set breakpoints -- -- Yes
    Step into, Step out-of, Step over lines -- -- Yes
    Break at (and continue from) ASSERT statements -- -- Yes
    Force/Release signals (create stimulus) -- -- Yes
Code-Coverage
    Fast code coverage (< 5% performance penalty) -- -- Yes
    Code-Coverage annotation in text editor -- -- Yes
    Collect coverage data over multiple runs -- -- Yes
    View Coverage data graphically -- -- Yes
    Convert coverage data to text report file -- -- Yes
    Convert coverage data to HTML report file -- -- Yes
Support
    Priority technical support -- Yes Yes
    Web based technical support Yes Yes Yes

Notes:

  1. Vital Libraries supplied by vendors (such as Xilinx or Altera) contain Vital Models that are LEVEL1 compliant. But within these libraries, there are a few complex components (like multipliers, PLLs, memories) that may only be LEVEL0 compliant. VHDL Simili is one of the few simulators that offers Acceleration for both LEVEL0 and LEVEL1 models whereas most other simulators typically only accelerate LEVEL1 models.
 

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